RISC-V processors can now use Android, thanks to this port

RISC-V  (pronounced “Risk-Five”) is a free hardware instruction set architecture (ISA) based on a RISC (reduced instruction set) type design.

Unlike other processors, RISC-V is free and open, thus allowing anyone to design and manufacture circuits by implementing them and even developing software for them.

It should be noted that they have a set of support software which avoids a common weakness in the new system of instructions that it implements. The project began in 2010 at the University of California at Berkeley, but many contributors are volunteers and industry workers outside of the university.

It is designed with small, fast, and low-power deployments in mind for the real world.

Well having a little knowledge of these processors, we continue with the following information of interest:

Recently, a few weeks ago, the Chinese chip manufacturer company T-Head (owned by alibaba), announced the important migration of the android 10 platform to the board architecture that implements these RISC-V processors.

An important feature of the new port is to provide support for graphics and touchscreens, as well as working on real hardware. In parallel, the PLCT Lab project is also involved in Android porting for RISC-V, which in the fall of last year managed to load the minimal system environment in console mode using an emulator.

T-Head has compiled Android 10 on the RISC-V architecture. The main reason for Android is to create an open software platform available to operators, OEMs and developers to bring their innovative ideas to life and present a successful real-world product that enhances users’ mobile experience.

In this new one an ICE EVB board is shown provided with the following 2 XuanTie C910 1.2GHz processors (RISC-V 64), With a XuanTie C910V core for vector processing a very powerful GPU that accepts hardware accelerated decoding of HEVC formats, AVC and JPEG.

T-Head C910 is a very high-performance 64-bit RISC-V compliant processor that offers performance that not many companies can compete with and is an industry leader in frequency, compute and control flow through the innovation of architecture and micro-architecture, The C910 processors are based on RV64GCV instruction sets and have and implement TIE technology.

In the future, T-HAED is expected to start manufacturing boards with RISC-V processors that can be used in multimedia devices such as smart TVs, tablets and even smartphones.

For those who do not know RISC-V, they should only know that it provides an open and flexible machine instruction system that allows creating microprocessors for applications of different purposes without requiring any type of payment for licenses or imposing conditions of use. RISC-V allows you to create completely open processors and SoCs.

RISC-V-logo.svg

Currently, on the basis of the RISC-V specification, several companies and communities under various free licenses (BSD, MIT, Apache 2.0) are developing several dozen variants of microprocessor cores, around a hundred SoCs and chips already produced. RISC-V support has been around since Glibc 2.27, binutils 2.30, gcc 7, and Linux kernel 4.15.

The hard work of developers from the world of free software and hardware to achieve the great advances that are being obtained in RISC-V should be highlighted to a great extent.

ICE EVB is a high performance SoC board based on XuanTie C910 developed by T-Head. The ICE SoC has integrated 3 XuanTie C910 (RISC-V 64) cores and 1 GPU core; with speed and intelligence with a high cost-benefit ratio. The chip can provide 4K @ 60 HEVC / AVC / JPEG decoding capability and varieties of high-speed interfaces and peripherals for data exchange and control; Suitable for 3D graphics, visual AI, and multimedia processing.

As for the port, we can find that the patches are prepared for the Android Open Source Project code base (or better known as AOSP) and cover several subsystems, including the graphics stack, the bionic library, the dalvik virtual machine and frames.

For those who are interested in the port, they can find a script to create AOSP for RISC-V devices or run it in an emulator you can check the following link.

In addition, the creation by BeagleBoard and Seeed of a new BeagleV board, built on a StarFive VIC7100 dual-core processor with RISC-V architecture, also stands out.

The board is specially developed for mass production of RISC-V computers with Linux-based software bloat, although personally it would be nice if other operating systems such as GNU / Hurd, FreeBSD, Plan9 are supported.

StarFive VIC7100 processor clocked at 1.5 GHz, includes MMUs and other components required for full Linux distributions and supports vector extensions, includes NNE (Neural Network Engine) and NVDLA (Nvidia Deep Learning Accelerator) engines to accelerate learning systems Automatic, DSP Tensilica VP6 for Accelerate computer vision processing and hardware H264, H265, JPEG (4K @ 60FPS) encoders / decoders.

The board is equipped with 8 GB of RAM, WiFi, Bluetooth, 4 USB 3.0 ports, USB-C, Gigabit Ethernet, HDMI 1.4, TF card slot, two MIPI-CSI (Serial Camera Interface) slots and one MIPI-DSI 40-pin GPIO.

In this way, it is demonstrated that in the world free software and free hardware there are significant projects that can be overcrowded without the known restrictions of proprietary licenses and patents where they only give exclusivity to certain companies and authorized persons in this regard, imposing certain limitations on other companies, which will not necessarily be direct competitors for the manufacturers of said devices, but rather they can develop other hardware elements that cover other branches of the market, helping in a very significant way to technological advancement and allowing the learning and manipulation of these technologies since we are in a society where knowledge should be available to everyone, many companies are already opening their eyes and are increasingly supporting the world of free software and hardware since the benefits are greater than working in a hermetic and closed way.

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